1. Field of the Invention
This invention relates generally to universal fuse latch circuits and, more particularly, to a new universal laser fuse/anti-fuse latch circuit and redundancy applications therefor.
2. Discussion of the Prior Art
FIG. 1 illustrates a prior art fuse latch circuit 10 comprising a fuse element 12 shown connected to strobe device (transistor) T7, and to a latch circuit formed by transistors T1, T2, T3 and inverter device 14. A latch precharge device (transistor) T6 is also shown connected to a power supply and a terminal of T7. In this circuit 10, a metal or other conductive material fuse element 12 is used to indicate one of two logical states. For example, if left intact, the latch will indicate a first logical state, or if programmed by laser oblation it may indicate a second logical state. The latch circuit 10 is typically used to equate these two opposite conductive states to opposite logical states. That is, the latch circuit 10 converts the fuse""s resistive levels into an electrical voltage level indicative of a logical 1 or 0.
A typical fuse read operation performed by the latch circuit 10 of FIG. 1 is implemented as follows: First, the precharge transistor device T6 is pulsed by signal 31 to precharge the latch 10 to a first logical state. Subsequently, the strobe device T7 is pulsed on by signal 22. If the fuse element is intact, it is conductive and drains off the precharge voltage from the latch node and forces it to a second logical state. Discharge of the latch""s preconditioning is made easier by disconnecting the cross-coupling when the strobe device is active which is accomplished by series device T2. If the fuse element 12 has been programmed, it no longer conducts enough to drain sufficient charge off the latch node to change the logical state of the latch. In this case, when the strobe device is activated, the latch remains in its first logical state.
It is often desirable for the fuse latch device 10 to be able to store a logical state indicative of the logical state of the fuse so that when the latch is then connected to other circuits, it may provide programming information for other electronic circuits such as address relocation for redundant memory elements, operating mode configuration, and to store a tracking code pertaining to manufacture date or other conditions, for example. U.S. Pat. No. 5,345,110 to Renfro (Micron Inc.) describes a similar fuse latch device. Additionally, U.S. Pat. No. 5,956,282 Casper (Micron Inc.) describes a prior art anti-fuse latch that is large, cumbersome and has no means to multiplex between traditional laser fuses, electrically oblated fuses and anti-fuse elements.
As the semiconductor industry replaces the traditional laser fuse technology with more flexible and denser electrically programmable xe2x80x9ceFUSExe2x80x9d elements, there is a need for a fuse latch capable of operating with both the old and new technology.
Traditional laser fuses have an unprogrammed resistance of less than 10 ohms, and a programmed resistance of greater than 100,000 ohm. Hence, a fuse latch which is designed with a resistive trip point of 10,000 ohms will function properly with adequate manufacturing margin of 10X. An unprogrammed electrical fuse may have a resistance of 100 ohms, which may increase to 100,000-ohms or higher when successfully programmed. If an electrical fuse which, when programmed, has less than 3-orders of magnitude resistance change, it may present a reliability problem and may need to be re-programmed or screened out. It is, therefore, desirable to have different latch trip resistances for different fuse, or anti-fuse types.
Further, as technology develops, evaluation of various electronic fuse types must be made while preserving the existing, and proven laser fuse circuitry. The evaluation of novel fuse structures, along side existing and proven fuse technology, has increased chip size. A fuse latch which can function with various fuse types, e.g., 1) existing laser fuses, 2) normally open-circuit xe2x80x9canti-fusesxe2x80x9d, and 3) normally short-circuit conductive-link fuses, is highly desirable.
While separate fuse latches may be designed with different latch feedback strengths to achieve various resistance trip points, latch area efficiently becomes significantly decreased. Alternately, a latch with an intermediate trip point may be designed as a compromise, but will likely cause yield loss as the latch is not optimized for either fuse type. Thus, it would be further desirable to provide a single universal fuse latch circuit design that provides flexibility to program and utilize various fuse types and, minimize the die size.
It would be further highly desirable to provide a control device for a universal fuse latch circuit that is flexible and enables simple and automatic selection of the type of fuse to use in the universal fuse latch circuit.
It is an object of this invention to provide a universal fuse latch circuit which is capable of sensing several types of fuse and anti-fuse elements.
It is another object of this invention to connect several legs or conductive paths to the universal fuse latch circuit to provide varying amounts of fuse resistance that may be required to trip the state of the fuse latch.
It is a further object of this invention to provide a fuse latch which has separate fuse resistance trip points for different fuse technologies to insure adequate programming of each fuse type.
It is yet another object of the present invention to provide a control device for a universal fuse latch circuit that is flexible and enables simple and automatic selection of the type of fuse to use in the universal fuse latch circuit.
It is still another object of this invention to provide a means to use a laser programmed fuse type by logical selection, and a second electrical fuse or anti-fuse element by a second logical selection.
It is yet a further object of this invention to provide a programmable fuse bank that implements information fuse latches each comprising a universal fuse latch circuit that may store information in one of legs comprising fuse type elements or legs comprising anti-fuse type elements, and a flexible mechanism for interrogating the information fuse latches.
Thus, according to the principles of the invention, there is provided a universal fuse latch device comprising a latch circuit receiving a precharge signal and latching the precharge signal at a latch node thereof for initializing the latch to a first state; and one or more legs connected at the latch node, with a first leg implementing a fuse type element capable of transitioning the latch from the first state to a second state, and a second leg including an anti-fuse type element, wherein the fuse latch is provided with a fuse resistance trip point to ensure adequate programming of one of the fuse and anti-fuse type element.
In one application, the universal fuse latch device is implemented as part of a programmable fuse bank comprising a plurality of information fuse latches for storing redundancy information in a memory system and capable of being simultaneously interrogated. A master fuse control device comprising the universal fuse latch circuit is provided that is programmed in accordance with a priority of legs to be interrogated in the information fuse latches. The system and method of the invention implements logic circuits and devices for determining the priority of legs that are to be interrogated for accessing the redundancy information and for generating appropriate interrogation strobe and leg selection signals to enable proper interrogation of the information fuse latches according to the determined priority while preventing simultaneous interrogation of each first leg and second leg of each of the plurality of programmed information fuse latches.
Advantageously, the provision of a universal fuse latch circuit capable of sensing several types of fuse and anti-fuse elements minimizes die size. Furthermore, the system and method of the invention is particularly applicable for improving dynamic random access memory (DRAM) and embedded DRAM (eDRAM) single cell fixability and flexibility repair at the module level.